This application claims the priority benefit of Taiwan application serial no. 88100242, filed Jan. 8, 1999, the full disclosure of which is incorporated herein by reference.
1. Field of Invention
The present invention relates to a memory accessing system and controlling method. More particularly, the present invention relates to a memory accessing and controlling system capable of shortening cross-bank and cross-page data access for a central processing unit (CPU).
2. Description of Related Art
Due to the rapid progress in computer technology, the operating speeds of most computer systems are very fast. Aside from a general increase in the working frequency of a CPU, the efficiency of other associated components inside a computer also increase correspondingly. For example, the accessing rate of a main memory such as a dynamic access memory (DRAM) in a computer system has increased. Furthermore, the method of memory control has also improved tremendously. Fast page mode (FPM) and extended data out (EDO) mode of operation have been developed from the earlier version of DRAM control. Now, the most popular memory control methods is the synchronized DRAM (SDRAM).
FIG. 1 is a block diagram showing a computer system having a conventional data accessing and controlling unit. The computer system includes a CPU 110, a data accessing and controlling unit 120 and a memory cluster 130. Through the data accessing and controlling unit 120, the CPU 110 is able to access the memory cluster 130. One end of the data accessing and controlling unit 120 has a few signaling lines that couple with the CPU 110. Similarly, the other end of the data accessing and controlling unit 120 has a few signaling lines that couple with the memory cluster 130. The memory cluster 130 itself contains a plurality of memory banks. In FIG. 1, for example, there are altogether four memory banks 140xcx9c143. In addition, each memory bank is further subdivided into a multiple of memory pages. For example, there are a few memory pages 150 within the memory bank 140 and the same number of memory pages in other memory banks as well. Furthermore, these memory banks may be divided into groups with each group enclosed within a memory module. In FIG. 1, memory banks 140 and 141 belong to a first memory module 131 whereas memory banks 142 and 143 belong to a second memory module 132.
The CPU 110 needs to access data in the memory cluster 130 through the data accessing and controlling unit 120. Therefore, the unit 120 must be able to receive a request signal from the CPU 110 and then produce appropriate controlling signals to the memory cluster 130. Otherwise, the CPU 110 is unable to write into or retrieve from the memory cluster 130.
The data accessing and controlling unit 120 is further divided into a CPU interface circuit 121 and a memory controlling circuit 122. The CPU interface circuit 121 is responsible for processing the signals coming from and transmitting to the CPU 110. When the CPU 110 needs to access the memory cluster 130, a data request signal is sent from the CPU 110 to the CPU interface circuit 121. Next, a signal is sent from the CPU interface circuit 121 to the memory controlling circuit 122. Finally, a signal is sent from the memory controlling circuit 122 to the memory cluster 130. Consequently, data from the CPU 110 can be written into the memory cluster 130 or data can be read from the memory cluster 130 by the CPU 110.
Signal lines that link the CPU interface circuit 121 with the CPU 110 include ADS, REQ, HITM, HD, DRDY and DBSY. A signal on the ADS line comes from the CPU 110. A low voltage in the ADS line represents that a request signal is to be sent out by the CPU 110 to access data. Then a signal on the REQ line is sent by the CPU 110 to request reading from or writing to the memory cluster 130. A signal on the HITM line represents that data stored in a cache memory (not shown) of the CPU 110 are to be written back to the memory cluster 130. Signals DRDY and DBSY are data ready and data busy signals, respectively. Both the DRDY and the DBSY signals are sent by the CPU interface circuit 121 to the CPU 110. When the DRDY and the DBSY lines are both at low potential, data are desired to be sent to the CPU 110 through the HD lines.
Signal lines that link the CPU interface circuit 121 with the memory controlling circuit 122 include DADS and DAT. A signal on the DADS line reciprocates the signal produced by the ADS signal from the CPU 110. The DAT lines are just data lines.
Signal lines that link the memory controlling circuit 122 with the memory cluster 130 include CS0xcx9cCS3, CMDBK0, CMBDK1 and MD. The signal lines CS0xcx9cCS3 are lines for selecting a particular memory bank from the memory banks 140xcx9c143. The signals CMDBK0 and CMDBK1 are instructions to memory modules 131 and 132, respectively. The MD lines are just data lines.
In general, depending on the user, different amounts of memory is installed in different computer systems. As a computer system is cold-started, the memory-controlling circuits initiate a series of steps checking the quantity of memory within the system and then retain a record of the memory status. For example, the address of each memory bank or memory page is recorded. Hence, if a particular piece of data that the CPU wants to access resides in a different memory page, the memory controlling circuit is able to issue related instructions for opening up the required page.
Since a record of the memory state is only kept in the memory controlling circuit, when the memory controlling circuit is controlling the memory, the next accessing operation is carried out only after the former accessing operation is completed. Therefore, the memory access rate is lower when cross memory page or cross memory bank data are required by the CPU.
In light of the foregoing, there is a need to provide a memory accessing and controlling system capable of shortening cross memory bank and cross memory page data access for a CPU.
Accordingly, the purpose of the present invention is to provide a data accessing and controlling unit capable of shortening a latency period for cross memory bank and cross memory page data access, thereby increasing overall efficiency of the system.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a data accessing and controlling unit capable of cross-bank and cross-page data access. The system is coupled to a CPU and a memory cluster. The memory cluster includes a plurality of memory banks with each memory bank having a plurality of pages. The CPU accesses data in the memory cluster through the data accessing and controlling unit. Internally, the data accessing and controlling unit can be further divided into a CPU interface circuit and a memory controlling circuit.
The CPU interface circuit is coupled to the CPU and the memory controlling circuit, and the memory controlling circuit is coupled to the memory cluster.
Operation of the data accessing and controlling unit is as follows. First, when the CPU sends out a data access request, an internal data access request is accordingly submitted by the CPU interface circuit to the memory controlling circuit. When the addresses of consecutive data access requests issued by the CPU are from different memory banks, a cross memory bank signal is also emitted by the CPU interface circuit along with the internal access request. Furthermore, when the addresses of consecutive data access requested by the CPU are from the same memory bank but a different memory page, a cross memory page signal is also emitted by the CPU interface circuit in addition to the internal data access request. The access request can be a request for reading data from the memory cluster or writing data to the memory cluster.
In the subsequent step, the memory controlling circuit acts according to the internal access request signals issued by the CPU interface circuit. When the memory controlling circuit receives both an internal access request signal and a cross memory bank or cross memory page signal, the memory page specifically addressed is opened immediately.
According to one preferred embodiment of this invention, the data accessing and controlling unit further includes an address register for storing the address data of various memory banks and memory pages. The CPU interface circuit sends out a cross memory bank or a cross memory page signal depending on the address data stored in the register. The address data inside the address register is constantly updated by monitoring the operations of the memory controlling circuit on the memory cluster.
In addition, the address register can reside within the CPU interface circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.